Logic Design Draw - A hierarchical WYSIWYG tool that enables a user to interactively create a logic schematic diagram and to run circuit simulation. Logic circuits can be very simple, such as and-or logic, or can consist of hundreds of parts. Both basic parts (logic gates, flip-flops) and MSI (Medium Scale Integration) building blocks are provided. Using blocks, large hierarchical designs - such as small computers - can be built. Computer Logic Simulation - Evaluates both logic circuit functionality and timing problems such as flip-flop setup and hold times, race conditions and glitches/spikes. All circuit types and configurations are supported: Combinational, Sequential, Synchronous and Asynchronous. Logic Design Auto - Automatically design small digital logic circuits and state machines from timing diagrams or truth tables. Boolean - Generates minimized Boolean equations from Boolean equation or Truth table inputs. Boolean operator formats are supported for a variety of languages including: ABEL, C, C++, PALASM, VB, Verilog and VHDL. The software uses both Quine-McCluskey and Espresso (UC Berkeley) algorithms to optimize minimization. Permutation - Generates permutations of numbers from a specified base number and a specified number of digits. Can be used for a variety of applications such as generating binary, octal or decimal number tables. Random Number - Generates from 1-99,999 random numbers in a specified range between -99,999 to 99,999.
What's new in this version:
Version 5.3.1 disables the weekly "New Version Available" check which may cause a false Firewall Error.